Published Oct 11, 2026 · Last updated Oct 11, 2026 · 4 min · IndieRF
50 Ω Microstrip Width on 1.6 mm FR-4
On FR-4 with εr 4.4, a 50 Ω microstrip at 1 GHz is 118.43 mil (3.008 mm) on 1.6 mm dielectric and 14.72 mil (0.374 mm) over a 0.2104 mm 7628 prepreg. The height to the ground sets the width.
On this library’s FR-4, εr 4.4, a 50 Ω microstrip at 1 GHz is 118.43 mil wide, 3.008 mm, when the dielectric is the full 1.6 mm of a two-layer board, the copper is 1 oz, and there is no solder mask. The same 50 Ω over a 0.2104 mm 7628 prepreg, the usual outer dielectric on a 1.6 mm four-layer board, is 14.72 mil, 0.374 mm. A trace drawn at 3.000 mm on the two-layer board reads 50.08 Ω. The height to the nearest ground sets the width. The finished board thickness does not.
The numbers are Hammerstad–Jensen Z0 with the Kirschning–Jansen correction at 1 GHz, from the same solver as the microstrip calculator.
How wide is 50 Ω microstrip on 1.6 mm FR-4?
Normalize the geometry before you quote a width. for this line is 1.88, inside the window. εeff at 1 GHz is 3.345. The TE1 estimate, , is 50.81 GHz, so 1 GHz is not where this closed form falls over.
| Stackup | Width | W/h | εeff | Z0 |
|---|---|---|---|---|
| 2-layer, 1.6 mm dielectric | 118.43 mil (3.008 mm) | 1.88 | 3.345 | 50.00 Ω |
| 4-layer 7628, 0.2104 mm | 14.72 mil (0.374 mm) | 1.78 | 3.332 | 50.00 Ω |
| 7628 pressed, 7.1 mil | 12.50 mil (0.317 mm) | 1.76 | 3.332 | 50.00 Ω |
| 4-layer 3313, 0.0994 mm | 6.56 mil (0.167 mm) | 1.68 | 3.331 | 50.00 Ω |
| 2-layer, width fixed at 3.000 mm | 118.11 mil (3.000 mm) | 1.87 | 3.344 | 50.08 Ω |
The 1.6 mm row is why a two-layer 50 Ω feed looks like a pour. At 3.008 mm it is wider than many SMA launches and wider than the keep-out next to a chip antenna. If the run is short compared with a wavelength you may not need the width. The delay note has the quarter-wave length. If the run is long, the width is the layout problem, and a coplanar gap is the usual way off this board. That comparison is microstrip vs GCPW vs stripline.
What about a 4-layer board?
A four-layer 1.6 mm stackup still finishes at 1.6 mm. The microstrip does not see that. It sees the prepreg between the outer copper and the ground on layer 2.
Two published heights, from JLCPCB’s 1.6 mm impedance stackups, are in the table. 7628 prepreg is 0.2104 mm nominal. 3313 prepreg is 0.0994 mm nominal. JLCPCB also tells you to use 7.1 mil, not the nominal 0.2104 mm, as the pressed thickness when the controlled-impedance tracks are on the outer layer of a 7628 stack. That row is 12.50 mil, 0.317 mm. I am using their published thicknesses and this library’s εr 4.4. Their process Dk for the core they actually press is not 4.4. If the fab gives you a Dk, put it in the calculator as a custom substrate before you freeze the width.
The thin rows are ordinary trace widths. 14.72 mil on 7628 is a normal 50 Ω rule. 6.56 mil (0.167 mm) on 3313 is getting tight for a loose etch tolerance, which is a fab question, not a reason to go back to 3 mm. Copper weight and solder mask move these thin lines more than they move the 1.6 mm line. That shift is how copper and solder mask change Z0.
Is a 3 mm trace close enough?
On this stackup, yes, if “close enough” means a few tenths of an ohm. The fixed 3.000 mm row is 50.08 Ω at 1 GHz. The solved width is 3.008 mm. I would not chase the 0.008 mm. I would chase the Dk the fab presses, the finished copper, and whether the mask is flooded.
εr 4.4 is a round IPC-4101-class value for “standard FR-4” in this library, with tanδ 0.02. A datasheet Dk of 4.2 or 4.6 moves the width more than the difference between 3.000 mm and 3.008 mm. The calculator will take that Dk. This note will not pretend one FR-4 number covers every glass style.
What this width is not
It is not a differential pair. 90 Ω and 100 Ω pairs are not solved here. It is not an ENIG correction: plating changes loss and, in this model, not Z0. It is not the impedance at 10 GHz. Dispersion on the 1.6 mm line pulls this same width off 50 Ω as frequency rises, which is the subject of effective permittivity and trace delay.
The model is quasi-TEM, not a stackup field solver. Solder mask, if you turn it on, is a capacitance overlay. Trust the width inside and below the TE1 figure. If the coupon disagrees, believe the coupon and the fab’s Dk.
References
- E. Hammerstad and Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” IEEE MTT-S International Microwave Symposium Digest, 1980. Static Z0 and εeff(0), with the thickness correction.
- M. Kirschning and R. H. Jansen, “Accurate model for effective dielectric constant of microstrip with validity up to millimetre-wave frequencies,” Electronics Letters, vol. 18, no. 6, pp. 272–273, 1982.
- IPC-4101. The εr 4.4 and tanδ 0.02 used here are this library’s standard-FR-4 values under that citation, not a controlled-impedance Dk from a fab.
- JLCPCB published 1.6 mm four-layer impedance stackups: 7628 prepreg 0.2104 mm, 3313 prepreg 0.0994 mm, and the note to use 7.1 mil for outer-layer tracks on 7628. Heights only. Their material Dk is not the 4.4 used above.
Related
- Microstrip vs GCPW vs stripline
- How copper and solder mask shift Z0
- Effective permittivity and trace delay
- Microstrip calculator
FAQ
How wide is a 50 ohm trace on 1.6 mm FR-4?
On this calculator’s FR-4 (εr 4.4), a 50 Ω microstrip at 1 GHz is 118.43 mil wide, 3.008 mm, with 1 oz copper and no solder mask. The dielectric height is the full 1.6 mm. A trace drawn at 3.000 mm on the same board reads 50.08 Ω.
How wide is 50 ohm microstrip on a 4-layer FR-4 board?
Use the dielectric height to the nearest ground, not the 1.6 mm finished thickness. Over a 0.2104 mm 7628 prepreg the 50 Ω width is 14.72 mil (0.374 mm). Over a 0.0994 mm 3313 prepreg it is 6.56 mil (0.167 mm). JLCPCB’s published pressed thickness for a top-layer 7628, 7.1 mil, solves to 12.50 mil (0.317 mm). These use εr 4.4, not a fab’s process Dk.
Does the model include solder mask and plating?
The width table is bare copper with the mask off, so it is the Hammerstad–Jensen line before those corrections. Solder mask and copper weight do move Z0. ENIG does not move Z0 in this model. That comparison is on the copper and solder-mask note.
What formula is the width?
Hammerstad and Jensen, IEEE MTT-S 1980, for static Z0 and εeff(0), including the thickness correction, then Kirschning and Jansen, Electronics Letters 1982, for εeff at 1 GHz. It is a closed-form quasi-TEM model, trustworthy roughly for 0.1 < W/h < 10 and below the TE1 estimate. On the 1.6 mm board that cutoff is 50.81 GHz.
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