IndieRF Transmission Line Calculator
Grounded coplanar waveguide calculator
Ghione–Naldi conductor-backed mapping plus finite ground width. Gap S and plating on the sidewalls dominate high-frequency conductor loss.
IndieRF Transmission Line Calculator
PCB traces and chip-and-wire
Mask t (um)
Relief (mil)
Loss sweep · dB/in
X GHz
Y dB
Loss breakdown @ eval
- Base Cu31.5%
- Plating49.5%
- Roughness11.1%
- Dielectric7.6%
- Mask0.3%
Skin depth vs plating
99.8% of current in the plating shell, 0.2% in the copper core.
Foil Reverse treated (RTF): Rq = 1.2 um · Huray a = 0.7 um, As/Af = 1.4
- Goldt=0.05 um · δ=0.79 um · 6.2%
σ = 4.10e7 S/m
- Nickelt=4.50 um · δ=0.72 um · 93.7%
σ = 1.40e7 S/m · μr = 3.5
- Copper coret=17.50 um · δ=0.66 um · 0.2%
σ = 5.80e7 S/m
What grounded coplanar waveguide is
A GCPW trace sits in a gap between two ground pours, with another ground on the back of the core. Energy is in both the slots and the dielectric under the strip. Narrowing the gap lowers Z0 and crowds current onto the slot edges, which is why plating thickness on the sidewalls shows up in the loss and barely, if at all, in this impedance formula.
Microstrip puts the return entirely on the backside plane, so a 50 Ω strip gets wide as the core gets thick. GCPW can stay narrow on that same core because the slot capacitance sets the impedance. The cost is a mode you have to short out with vias, and a width that moves when the etch changes S by a mil.
Conformal-mapping model
Impedance and εeff come from Ghione and Naldi’s conductor-backed map (IEEE Trans. MTT, vol. 35, pp. 260–267, 1987), including finite ground width. With the complete elliptic integral K:
- k3 = tanh(πW / 4h) / tanh(π(W + 2S) / 4h)
- k∞ = W / (W + 2S), k2 = (W + 2S) / (W + 2S + 2G)
- k = k∞ · sqrt((1 − k2²) / (1 − k∞² · k2²))
- Z0 = 60π / (sqrt(εeff) · (K(k)/K′(k) + K(k3)/K′(k3)))
εeff is the parallel combination of an air capacitance and a dielectric capacitance, written (1 + εr·ρ) / (1 + ρ), where ρ is the ratio of the backed elliptic term to the coplanar one. As G becomes large, k approaches k∞. Conductor thickness is absent from W in this Z0. The loss model still uses t, through a geometry factor 1 + h/W + 0.35·t/S, and it assigns 60% of the signal current to the plated surfaces. Dispersion above the static map is Getsinger’s form, εeff(f) = εr − (εr − εeff(0)) / (1 + (f/fc)²), with fc taken from the microstrip TE1 estimate. That is a smooth correction, not a full-wave GCPW mode solution.
50 Ω examples on FR-4 and RO4350B
Each GCPW width is the static map locked to 50 Ω within 0.01 Ω. Bare copper, no solder mask. RO4350B uses the design Dk in this library, εr = 3.66, not the process Dk 3.48. FR-4 uses εr = 4.4. The microstrip column is Hammerstad–Jensen on the same core and copper weight, so it does include thickness; the GCPW column does not. The widget’s default ENIG stack and relieved solder mask add a further small shift on top of these widths.
| Stackup | h | S | G | GCPW W | εeff | Microstrip W |
|---|---|---|---|---|---|---|
| RO4350B εr 3.66 | 10.0 mil | 6.0 mil | 40.0 mil | 18.9 mil | 2.66 | 21.2 mil |
| RO4350B εr 3.66 | 20.0 mil | 8.0 mil | 80.0 mil | 33.9 mil | 2.58 | 42.4 mil |
| FR-4 εr 4.4 | 8.0 mil | 5.0 mil | 40.0 mil | 13.2 mil | 3.08 | 14.2 mil |
| FR-4 εr 4.4 | 1.6 mm (63.0 mil) | 10.0 mil | 100.0 mil | 60.0 mil | 2.83 | 118.9 mil |
Copper weight on the 10 mil RO4350B row is 0.5 oz (17.5 µm). The other rows are 1 oz (35 µm). Changing that weight does not move the GCPW width in this model. It does move the microstrip width, and it moves GCPW loss.
Via fence spacing
Conductor backing opens a parallel-plate path between the coplanar grounds and the backside plane. The slots can also launch a slotline mode if the two grounds are not tied. Vias are what make the structure match the equipotential assumption in the map. They are not a term in Z0 here.
Along the line, keep the via pitch at or under λg/8 at the highest frequency you care about, and tighter (toward λg/20) when the parallel-plate mode is already visible. Use λg = c / (f · sqrt(εr)), which assumes the unwanted mode is mostly in the dielectric. At 20 GHz on RO4350B that is 0.98 mm for λg/8 and 0.39 mm for λg/20. Across the line, put the first via row close to the gap — a practical start is two to three gap widths — so the ground between the slot and the stitch is not a stub. Two rows are safer than one when the pour is wide.
References
- G. Ghione and C. U. Naldi, “Coplanar Waveguides for MMIC Applications: Effect of Upper Shielding, Conductor Backing, Finite-Extent Ground Planes, and Line-to-Line Coupling,” IEEE Trans. Microwave Theory Tech., vol. 35, no. 3, pp. 260–267, Mar. 1987.
- G. Ghione and C. Naldi, “Parameters of coplanar waveguides with lower ground plane,” Electronics Letters, vol. 19, no. 18, pp. 734–735, 1983.
- W. J. Getsinger, “Microstrip dispersion model,” IEEE Trans. Microwave Theory Tech., vol. 21, no. 1, pp. 34–39, 1973. Used here only as the shape of εeff(f).
- B. C. Wadell, Transmission Line Design Handbook. The unbounded CPW elliptic form; the backed k3 above is the Ghione–Naldi extension.
FAQ
What is grounded coplanar waveguide?
Grounded coplanar waveguide (GCPW), also called conductor-backed CPW, is a strip with gaps to coplanar ground pours and a ground plane on the other side of the dielectric. Return current divides between the coplanar grounds and the backside plane. The gap S, more than the strip width alone, sets the impedance.
When should I use GCPW instead of microstrip?
Use GCPW when a 50 Ω microstrip would be wider than the layout allows, when shunt parts need a ground next to the trace, or when you are willing to via-stitch the grounds. On 1.6 mm FR-4 (εr 4.4) this model gives about 118.9 mil of microstrip width and about 60.0 mil of GCPW center width with a 10.0 mil gap. On 10 mil RO4350B (εr 3.66, design Dk 3.66) the two are close: about 21.2 mil of microstrip versus 18.9 mil of GCPW with a 6.0 mil gap. GCPW is more sensitive to etch of the gap, and the sidewalls carry a large share of the current.
What model does this grounded coplanar waveguide calculator use?
A zero-thickness conformal map. The backed modulus is k3 = tanh(πW/4h) / tanh(π(W+2S)/4h). Finite ground width G replaces the infinite-ground k = W/(W+2S) with k = k∞ · sqrt((1−k2²)/(1−k∞²·k2²)), where k2 = (W+2S)/(W+2S+2G). Then εeff = (1 + εr·ρ) / (1 + ρ) with ρ = [K(k3)/K'(k3)] / [K(k)/K'(k)], and Z0 = 60π / (sqrt(εeff) · (K(k)/K'(k) + K(k3)/K'(k3))). Copper thickness is not in that Z0. It enters only the loss geometry factor. Dispersion is a Getsinger slide of εeff from εeff(0) toward εr, using a microstrip-style TE1 estimate as the corner, not a GCPW dispersion paper.
How far apart should the GCPW via fence be?
The formula assumes the coplanar grounds and the backside ground are the same potential. It does not include vias, so the width it prints is the stitched-ground impedance, not a via-loaded one. Without a fence, conductor-backed CPW launches a parallel-plate mode from low frequency; that is a layout problem, not something the TE1 readout measures. A usual ceiling on via pitch along the line is λg/8 at the highest frequency, with λg = c / (f·sqrt(εr)) for a field mostly in the dielectric. At 20 GHz on RO4350B (εr 3.66) that pitch is 0.98 mm; λg/20 is 0.39 mm. Place the first row within a few gap widths of the slot, often two to three times S, so the pour between the gap and the via is not a long stub.
What are the limits of this GCPW calculation?
It is a quasi-TEM closed form, not a 3D solver. There is no etch compensation, no via inductance, and no bond-wire model. Solder mask is a small capacitance correction on top of the map. The cutoff figure reused here is fc ≈ c / (2h·sqrt(εr−1)), a surface-wave estimate, and it is not the frequency where the parallel-plate mode starts. Treat gap etch and via pitch as first-order layout errors. Treat the third digit of Z0 as the solver tolerance, not a fabrication tolerance.
A lumped match at the end of this line is a different tool. Open the Smith chart to design an L-network from a load impedance.