Does a Via Fence Change GCPW Impedance?

A via fence does not change the GCPW impedance this calculator prints. The Ghione–Naldi map assumes the coplanar grounds and the backside plane are already the same potential. There is no via in the formula. What moves Z0 is the gap. On 10 mil RO4350B, εr 3.66, 0.5 oz, no mask, a strip solved to 50.00 Ω at a 6 mil gap is 18.93 mil wide. Hold that width and a 4 mil gap reads 47.20 Ω. A 12 mil gap reads 53.87 Ω. Widen the pour from 40 mil to 200 mil and the same strip moves from 50.00 Ω to 49.78 Ω. The fence is how you make the board match the assumption. It is not a fourth dimension in Z0.

Does via spacing change the impedance this calculator prints?

No. Conductor-backed coplanar waveguide has a parallel-plate path between the top grounds and the backside plane, and a slotline mode if the two grounds are not tied. Vias are what short those modes. The solver never sees them. If the fence is missing, the board is a different circuit than the number on the screen, and no amount of precision in $S$ repairs that.

The width the tool prints is the stitched-ground impedance. Treat a sparse fence as a layout error, in the same class as an etch that opens the gap, not as a small fudge on the third digit.

How much does the gap move Z0?

The gap is the dimension people under-specify. A 6 mil gap and an 8 mil gap are both “about 6 mil” on a loose drawing. They are not the same line.

From 4 mil to 12 mil, at fixed width, Z0 runs from 47.20 Ω to 53.87 Ω. That is 6.67 Ω for an 8 mil change in a dimension the etch will move. If you need 50 Ω at a different gap, solve the width again. Do not scale the 6 mil result by hand.

At a 4 mil gap the 50 Ω width is 16.94 mil. At 12 mil it is 21.45 mil. Narrower gap, narrower strip, and more of the current on the slot edge, which is why the loss column in the topology comparison is higher for GCPW than for microstrip even before anyone counts radiation. This Z0 is still the zero-thickness map. Copper weight does not enter it. The 0.5 oz on this core is there for the loss model and so the link matches a real foil.

The same 6 mil gap at 1 GHz is the 18.93 mil row in the topology note. On a 10 mil core the gap moves Z0. Dispersion does not, at the scale of these mils.

When does the ground pour stop mattering?

$G$ is the width of each coplanar ground, from the gap outward. It is not the via pitch, and it is not the distance from the strip to the via.

At $G = 5$ mil the pour is a sliver and Z0 is 52.09 Ω. At 40 mil, about seven gap widths, it is 50.00 Ω. At 200 mil it is 49.78 Ω. Once the pour is wide compared with the gap, more copper barely moves the elliptic ratio. I size $G$ so the curve has already flattened, then I spend the remaining effort on the gap etch and on getting a via close to that gap. A practical start for the first via row is two to three gap widths off the slot, so the copper between the gap and the stitch is not a stub. That distance is still not inside Z0.

How far apart should the vias be, then?

Along the line, a usual ceiling is $\lambda_g/8$ at the highest frequency you care about, and tighter, toward $\lambda_g/20$, when the parallel-plate mode is already visible. Use $\lambda_g = c / (f \sqrt{\varepsilon_r})$, which assumes the unwanted field is mostly in the dielectric. At 10 GHz on this RO4350B, εr 3.66, $\lambda_g/8$ is 1.96 mm and $\lambda_g/20$ is 0.78 mm. At 20 GHz those are 0.98 mm and 0.39 mm. The table under the gap chart has both.

This length does not come back out of the impedance solver. Two boards with the same $W$, $S$, and $G$, and different via pitches, get the same Z0 from this calculator. They will not measure the same if one pitch is a large fraction of $\lambda_g$.

What this model is not

It is not a via model, a bond-wire model, or an etch model. It is not 3D. Solder mask, if you turn it on, is a small capacitance on top of the map. The cutoff figure reused from microstrip, $c / (2 h \sqrt{\varepsilon_r - 1})$, is a surface-wave estimate. It is not the frequency where the parallel-plate mode starts. That mode starts as soon as the planes are not tied.

Ghione and Naldi’s $k_3 = \tanh(\pi W/4h) / \tanh(\pi(W+2S)/4h)$ is the backed term. Finite $G$ replaces the infinite-ground $k$ with the Hanna form. As $G$ grows, $k$ goes back to $W/(W+2S)$, which is what the flat part of the pour curve is showing.

If the fence is there, the gap is the number to put a tolerance on. If the fence is not there, fix the fence before you chase 0.2 Ω in $G$.

References

• G. Ghione and C. U. Naldi, “Coplanar Waveguides for MMIC Applications: Effect of Upper Shielding, Conductor Backing, Finite-Extent Ground Planes, and Line-to-Line Coupling,” IEEE Trans. Microwave Theory Tech., vol. 35, no. 3, pp. 260–267, Mar. 1987.
• G. Ghione and C. Naldi, “Parameters of coplanar waveguides with lower ground plane,” Electronics Letters, vol. 19, no. 18, pp. 734–735, 1983.
• B. C. Wadell, Transmission Line Design Handbook. The unbacked CPW form. The backed $k_3$ above is the Ghione–Naldi extension.

Related

• Microstrip vs GCPW vs stripline
• 50 Ω microstrip width on 1.6 mm FR-4
• GCPW calculator

FAQ

Do via fences change GCPW impedance?

Not in this calculator. The Ghione–Naldi map assumes the coplanar grounds and the backside plane are already the same potential. There is no via inductance. The width it prints is the stitched-ground impedance.

How does the GCPW gap change impedance?

On 10 mil RO4350B, a strip solved to 50.00 Ω at a 6 mil gap is 18.93 mil wide. Holding that width, a 4 mil gap reads 47.20 Ω and a 12 mil gap reads 53.87 Ω. Solving 50 Ω again, the width moves from 16.94 mil at a 4 mil gap to 21.45 mil at a 12 mil gap.

How wide should the GCPW ground pour be?

On that same 18.93 mil strip and 6 mil gap, G = 5 mil reads 52.09 Ω, G = 40 mil reads 50.00 Ω, and G = 200 mil reads 49.78 Ω. Past a few gap widths the pour stops moving Z0. This G is the copper width, not the via pitch.

How far apart should GCPW stitching vias be?

A usual ceiling is λg/8 along the line at the highest frequency, with λg = c / (f √εr), tighter toward λg/20 when a parallel-plate mode is already a problem. At 10 GHz on RO4350B (εr 3.66) λg/8 is 1.96 mm and λg/20 is 0.78 mm. That pitch is a layout rule. It is not an input to Z0.