Published Oct 11, 2026 · Last updated Oct 11, 2026 · 5 min · IndieRF
KiCad vs JLCPCB 50 Ω Microstrip Width
On JLC04161H-7628 this calculator’s 50 Ω microstrip at 1 GHz is 12.06 mil with JLCPCB’s 7.1 mil height, εr 4.4, 1.6 mil copper, and 0.6 mil mask. The 0.2104 mm drawing with 35 µm and no mask is 14.72 mil. KiCad’s manual does not publish those inputs.
On JLC04161H-7628, this calculator’s 50 Ω microstrip at 1 GHz is 12.06 mil wide, 0.306 mm. That row uses JLCPCB’s published numbers: 7.1 mil of 7628 over layer 2, εr 4.4, finished 1 oz copper of 1.6 mil, and solder mask 0.6 mil at εr 3.8. The same stackup with the mask off is 12.37 mil, 0.314 mm. Typing the drawing height of 0.2104 mm, this library’s εr 4.4, 35 µm copper, and no mask is 14.72 mil, 0.374 mm. The width moves because the inputs move.
KiCad 9’s PCB calculator does not publish a width I can cite. The TransLine section of the 9.0.9 manual says the calculator is heavily based on Transcalc, that the models are frequency-dependent, and that microstrip follows H. A. Atwater, Microwave Journal, November 1989. That section lists line types and references. It does not specify a solder mask, a dielectric constant, a copper thickness, or a fab stackup. This model is Hammerstad–Jensen with the Kirschning–Jansen correction. Even identical inputs can disagree. This note does not quantify that model gap, and it does not report a number from KiCad.
Open the JLC04161H-7628 preset. Bare copper, 1 GHz, locked to 50 Ω. W/h is 1.70. The TE1 estimate is 450.77 GHz.
What each row assumes
Scroll sideways for more columns
| Inputs | Width | εeff | Z0 |
|---|---|---|---|
| JLC04161H-7628 7.1 mil, εr 4.4, 1.6 mil copper, mask 0.6 mil at εr 3.8 | 12.06 mil (0.306 mm) | 3.418 | 50.00 Ω |
| Same stackup, mask off 7.1 mil, εr 4.4, 1.6 mil copper, no mask | 12.37 mil (0.314 mm) | 3.332 | 50.00 Ω |
| Drawing height, library FR-4 0.2104 mm, εr 4.4, 35 µm copper, no mask | 14.72 mil (0.374 mm) | 3.332 | 50.00 Ω |
| Older JLCPCB εr 7.1 mil, εr 4.6, 1.6 mil copper, mask 0.6 mil at εr 3.8 | 11.64 mil (0.296 mm) | 3.544 | 50.01 Ω |
| JLCPCB 2-layer 1.6 mm 1.6 mm finished, εr 4.5, 35 µm copper, mask 0.6 mil at εr 3.8 | 116.09 mil (2.949 mm) | 3.420 | 50.00 Ω |
| PCBWay 4-layer 1.6 mm, 70% 0.1855 mm, DK 4.74, 35 µm copper, mask off | 12.13 mil (0.308 mm) | 3.546 | 50.00 Ω |
JLCPCB’s current impedance page lists 7628 εr as 4.4, 3313 as 4.1, and 2116 as 4.16. The core is 4.6. No frequency is stated, so these rows are simply evaluated at 1 GHz. An older JLCPCB page still lists 7628 as 4.6. Using 4.6 with the rest of the current impedance inputs, 7.1 mil, 1.6 mil copper, and the mask, solves to 11.64 mil, 0.296 mm, at 50.01 Ω. The lock stops within 0.01 Ω.
The FR-4 width note has a 7.1 mil row at 12.50 mil, 0.317 mm. That row is εr 4.4, 35 µm, and no mask. Finished copper of 1.6 mil, still with the mask off, is the 12.37 mil row here. The stackup drawing’s 0.035 mm foil is not the 1.6 mil the impedance calculator uses.
Loss tangent is not on the stackup page. Every preset uses 0.02, this library’s FR-4 value. It is an assumption. It changes loss. The width solve is set by height, εr, copper, and the mask.
Two-layer and PCBWay
The JLCPCB 2-layer 1.6 mm preset solves to 116.09 mil, 2.949 mm. εr 4.5 is the capabilities table for a 2-layer board. Copper is 35 µm, from the 2-layer custom-PCB page. Mask εr 3.8 is published. The 0.6 mil mask thickness is the multilayer impedance figure, used here as an assumption, because the capabilities page only says the ink is at least 10 μm. The dielectric height is the finished 1.6 mm. JLCPCB does not publish the core thickness apart from that finished thickness, so that height is an assumption too. The unmasked εr 4.4 line on a full 1.6 mm in the FR-4 note is 118.43 mil.
PCBWay’s 1.6 mm 4-layer row at 70% residual copper is 12.13 mil, 0.308 mm. After lamination the 7628 is 0.1855 mm at DK 4.74, and 1 oz copper is 35 µm. Their impedance calculator says the outer-layer checks omit solder mask, and they do not publish a mask thickness or εr, so the preset turns the mask off. They also do not state a frequency for DK. A 2-layer PCBWay εr is not published. The preset uses 4.6, the core DK on the multilayer page, and says so.
What neither calculator should pretend
JLCPCB’s impedance guide says the etched top width is the base width minus 0.7 mil. This solver uses the width you type. It does not subtract 0.7 mil. PCBWay’s tolerance page lists a 0.01 mm etch compensation for 1 oz. That step is not applied either.
A four-layer stripline in this preset sits on layer 2. The dielectric above it and the core below it do not share one published εr. This calculator needs one εr, so it combines the two as series capacitors and labels that number an assumption. A two-layer preset has no inner layer, so it does not fill a stripline.
These rows are a closed-form check of the published stackup. They are not the fab’s coupon, and they are not a replacement for the fab’s impedance calculator.
References
- E. Hammerstad and Ø. Jensen, “Accurate Models for Microstrip Computer-Aided Design,” IEEE MTT-S International Microwave Symposium Digest, 1980.
- M. Kirschning and R. H. Jansen, “Accurate model for effective dielectric constant of microstrip with validity up to millimetre-wave frequencies,” Electronics Letters, vol. 18, no. 6, pp. 272–273, 1982.
- KiCad 9.0 PCB Calculator manual, TransLine section, based on KiCad 9.0.9. Accessed 2026-10-11. https://docs.kicad.org/9.0/en/pcb_calculator/pcb_calculator.html
- H. A. Atwater, “Simplified Design Equations for Microstrip Line Parameters,” Microwave Journal, pp. 109–115, November 1989. Cited by that KiCad page for microstrip.
- JLCPCB impedance stackup, including JLC04161H-7628 and the current εr table. Accessed 2026-10-11. https://jlcpcb.com/impedance
- JLCPCB impedance parameters, for the 7.1 mil outer / 8.1 mil inner 7628 instruction and the older εr table. Accessed 2026-10-11. https://cart.jlcpcb.com/client/template/placeOrder/impedance.html
- JLCPCB impedance calculator guide, updated 16 September 2026. Finished 1 oz copper 1.6 mil, mask 0.6 mil at εr 3.8, top width = base − 0.7 mil. Accessed 2026-10-11. https://jlcpcb.com/help/article/user-guide-to-the-jlcpcb-impedance-calculator
- JLCPCB capabilities. 2-layer FR-4 εr 4.5, mask εr 3.8, ink thickness only ≥ 10 μm. Accessed 2026-10-11. https://jlcpcb.com/capabilities/
- JLCPCB 2-layer custom PCB. Each copper layer 1 oz (35 μm). Accessed 2026-10-11. https://jlcpcb.com/resources/custom-pcb
- PCBWay multilayer stackup. 4-layer 1.6 mm, 1 oz, 70% residual copper: 7628 DK 4.74, 0.1855 mm after lamination. Accessed 2026-10-11. https://www.pcbway.com/multi-layer-laminated-structure.html
- PCBWay impedance calculator. Outer-layer checks omit solder mask. Accessed 2026-10-11. https://www.pcbway.com/pcb_prototype/impedance_calculator.html
- PCBWay manufacturing tolerances. 1 oz = 35 μm. 1 oz etch compensation 0.01 mm. No mask thickness or εr. Accessed 2026-10-11. https://www.pcbway.com/pcb_prototype/PCB_Manufacturing_tolerances.html
Related
- 90 Ω USB differential pair width
- 50 Ω microstrip width on 1.6 mm FR-4
- How copper and solder mask shift Z0
- JLC04161H-7628 in the calculator
- JLCPCB 2-layer 1.6 mm
- PCBWay 4-layer 1.6 mm, 70%
FAQ
Why do KiCad and JLCPCB print different 50 ohm widths?
On JLC04161H-7628 this calculator’s 50 Ω microstrip at 1 GHz is 12.06 mil when the inputs are JLCPCB’s published 7.1 mil height, 7628 εr 4.4, 1.6 mil finished copper, and 0.6 mil mask at εr 3.8. Typing the 0.2104 mm drawing, εr 4.4, 35 µm copper, and no mask makes it 14.72 mil. KiCad 9’s TransLine manual cites Atwater 1989 and does not specify mask, εr, copper thickness, or a fab stackup, so this note does not report a KiCad width.
How much does JLCPCB solder mask change the 50 ohm width?
On that same JLC04161H-7628 stackup, turning the mask off moves the 50 Ω width from 12.06 mil (0.306 mm) to 12.37 mil (0.314 mm). The mask in the preset is 0.6 mil at εr 3.8, from JLCPCB’s impedance calculator guide. Mask tanδ is not published. Loss keeps 0.02.
Should I use 7.1 mil or 0.2104 mm for JLCPCB 7628?
JLCPCB says to use 7.1 mil for an outer-layer controlled-impedance track on 7628. The stackup drawing lists 0.2104 mm. At εr 4.4, 35 µm, and no mask, 0.2104 mm solves to 14.72 mil. The 7.1 mil row in the FR-4 width note, still at 35 µm and no mask, is 12.50 mil. Finished 1 oz copper of 1.6 mil, with the mask off, is 12.37 mil.
Does this replace the JLCPCB impedance calculator?
No. It is a closed-form check of the published stackup in this model: Hammerstad–Jensen plus Kirschning–Jansen at 1 GHz. JLCPCB does not state the frequency of εr. Their guide also subtracts 0.7 mil from the base width for the etched top. This solver does not. Build from their coupon.
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